A conventional process step in the manufacturing of integrated circuits and devices involves plating a conductive layer on a semiconductor substrate. Plating the substrate with the conductive material over a seed layer has important and broad application in the semiconductor industry. Traditionally, aluminum and other metals are deposited as one of many conductive layers that make up a semiconductor chip. However, in recent times, there is great interest in copper deposition for interconnects on semiconductor chips, because, compared to aluminum, copper reduces electrical resistance and allows semiconductor chips to run faster with less heat generation, resulting in a significant gain in chip capacity and efficiency.
Typically, the semiconductor substrate has been previously etched and contains many holes and/or trenches on its surface. One goal of plating is to uniformly fill the holes and trenches with the conductive material.
However, as known in the art, conventional plating methods result in “dishing” or non-planar deposition during the plating process. In FIG. 1A, a barrier layer 4 and a seed layer 6 is disposed upon a substrate 2, where a section of the substrate 2 includes a trench 12. After forming the barrier layer 4 and the seed layer 6, a conductive layer 8 is plated on top of the seed layer 6. Because the trench 12 may be relatively large, a recess 10 is formed thereon and dishing results.
For small features with sub-micron size dimensions, existence of voids in the deposited conductive layer is a common problem. In FIG. 1B, such a void 14 is formed near the bottom of a narrow hole 16. It is well known that the existence of such voids in the deposited conductive layer results in defective devices with poor performance. Accordingly, the present invention provides a more accurate, fast, cost effective, and reliable manner of applying the conductive material to the semiconductor substrate.